You're evaluating three FPGAs for your next design. They all have enough logic elements, the right I/O, and compatible SerDes speeds. The datasheets list "typical" power numbers that look reasonable. You pick one, design the board, and during testing discover it pulls 40% more power than you expected. Your thermal solution is inadequate, your power supply is undersized, and you're respinning the board.
Sound familiar? FPGA power estimation is one of the least intuitive parts of device selection, and datasheet numbers are almost useless for real designs. Let's build a framework for estimating and comparing FPGA power consumption before you commit to silicon.
Why FPGA Power Numbers Lie (Sort Of)
FPGA vendors publish power numbers in their datasheets, but these are measured under very specific — and often unrealistic — conditions:
- Quiescent power at room temperature with no logic toggling
- "Typical" toggle rates of 12.5% or 25% that may not match your design
- Room temperature junctions (25°C), not the 85°C+ you'll see in practice
- Best-case process silicon, not the worst-case parts you might receive
The result: datasheet power numbers can be off by 2–3× compared to your actual design. Not because vendors are dishonest, but because your design's power depends on things the datasheet can't predict.
Static Power vs Dynamic Power
Total FPGA power has two components:
P_total = P_static + P_dynamic
Static power is what the FPGA consumes just sitting there, powered up, with no clocks running. It comes from transistor leakage and is strongly dependent on:
- Process node (smaller = more leakage)
- Junction temperature (higher = exponentially more leakage)
- Process variation (some chips leak more than others)
- Core voltage
Dynamic power comes from charging and discharging capacitance as logic switches. It depends on:
- Clock frequency
- Toggle rate of each signal
- Capacitance of the routing and logic
- Core voltage (dynamic power scales with V²)
P_dynamic = α × C × V² × f
Where α is the activity factor (toggle rate), C is capacitance, V is core voltage, and f is frequency.
The Process Node Paradox
Here's something that catches people off guard: migrating to a smaller process node increases static power while decreasing dynamic power. At 28nm and below, static power can easily be 30–50% of total power for designs that aren't running at maximum clock rates.
| Process Node | Static Power Trend | Dynamic Power Trend | Total Power Trend |
|---|---|---|---|
| 65nm | Low | High | High |
| 28nm | Moderate | Moderate | Moderate |
| 20nm | Higher | Lower | Similar or lower |
| 16nm/14nm | High | Lower | Depends on design |
| 7nm | Very high | Low | Lower (if clocked fast) |
If you're running a 50MHz control path on a 16nm FPGA, you might actually use more power than the same design on 28nm, because the static power dominates. Faster designs benefit more from advanced nodes because dynamic power savings outweigh the static power increase.
Estimating Static Power
Static power is the hardest thing to estimate without vendor tools because it varies so much with temperature and process. But you can get in the ballpark.
From Datasheet Specs
Most FPGA datasheets list static power (often called "standby power" or "quiescent power") at 25°C junction. To estimate at your operating temperature:
- Static power roughly doubles for every 15–20°C increase in junction temperature above 25°C
- At 85°C junction, expect 4–8× the 25°C datasheet number
- At 100°C junction, expect 8–16× the 25°C number
Yes, that's a huge range. That's why you need vendor power estimation tools for final design work.
Static Power Comparison (Typical, 25°C)
| Device Family | Process | Static Power (Lowest Density) | Static Power (Highest Density) |
|---|---|---|---|
| Lattice iCE40 | 40nm | ~1–5mW | ~10–50mW |
| Lattice ECP5 | 45nm | ~30–80mW | ~150–400mW |
| Lattice CrossLink-NX | 28nm | ~20–50mW | ~100–300mW |
| Intel Cyclone 10 GX | 20nm | ~100–300mW | ~400–1200mW |
| Intel Arria 10 | 20nm | ~300–800mW | ~1.5–4W |
| Xilinx Artix-7 | 28nm | ~80–150mW | ~200–500mW |
| Xilinx Kintex UltraScale | 20nm | ~200–500mW | ~800mW–2W |
| Xilinx Kintex UltraScale+ | 16nm | ~150–400mW | ~500mW–1.5W |
These are rough typical numbers at 25°C. Your actual static power at operating temperature could be several times higher.
Estimating Dynamic Power
Dynamic power is more predictable because you can estimate it from your design parameters.
The Quick Estimation Method
- Estimate your logic utilization — how many LUTs, FFs, DSP blocks, and BRAMs will your design use?
- Estimate toggle rates — control logic typically toggles at 5–15%, datapath at 15–30%, clock networks at 100%
- Apply vendor power coefficients — most vendors publish power per logic element per MHz
A rough formula for logic dynamic power:
P_logic ≈ N_LE × α × C_eff × V² × f
Where N_LE is the number of used logic elements, α is average toggle rate, C_eff is effective capacitance per element, V is core voltage, and f is clock frequency.
Practical Power Coefficients
Here are ballpark dynamic power coefficients for modern FPGAs:
| Resource | Approximate Power per MHz per Unit |
|---|---|
| LUT + FF pair | 1–5 μW/MHz |
| DSP block (18×18) | 5–20 μW/MHz |
| BRAM (18K or 36K) | 5–15 μW/MHz per port |
| SerDes (per lane) | 100–500 μW/MHz |
| PLL/MMCM | 50–150 mW (fixed) |
| I/O bank (LVCMOS) | 1–3 μW/MHz/pin |
Worked Example
Let's estimate power for a mid-range design on a Xilinx Kintex-7 (28nm):
- 20,000 LUTs used, 30% average toggle rate, 100MHz clock
- 10 DSP blocks, 50% utilization, 100MHz
- 20 BRAMs, single-port, 100MHz
- 1 SerDes lane at 6.25 Gbps
- Core voltage: 1.0V
P_logic = 20,000 × 0.30 × 3μW × 100 = 1.8W
P_dsp = 10 × 0.50 × 15μW × 100 = 0.075W
P_bram = 20 × 0.50 × 10μW × 100 = 0.1W
P_serdes = ~0.5W (typical for 6.25Gbps per lane)
P_pll = ~0.1W
Dynamic power total ≈ 2.6W
Add static power at 85°C junction — let's say the datasheet lists 200mW at 25°C for this density. At 85°C, that's roughly 200mW × 5 = 1W.
Total estimated power ≈ 3.6W
Is this accurate? Within maybe ±30%. Good enough to size your power supply and thermal solution with appropriate margin. Not good enough to skip vendor power analysis tools entirely.
The Temperature Snowball Effect
Here's a feedback loop that ruins designs: higher temperature → higher static power → more heat → higher temperature.
At low static power levels (sub-100mW), this effect is negligible. At higher levels (1W+ static), it can push your junction temperature 10–20°C higher than a simple linear calculation would predict.
Mitigation strategies:
- Over-size your heatsink by 20–30% beyond what the initial calculation suggests
- Use thermal simulation (most vendors provide tools) for designs with >2W static power
- Consider lower-density parts if you don't need all the logic — smaller dies have lower static power
- Some FPGAs support lowering core voltage to reduce both static and dynamic power (at the cost of maximum frequency)
Power Comparison Framework
When comparing FPGAs for a design, use this checklist:
- Calculate static power at your worst-case junction temperature (not 25°C)
- Estimate dynamic power from your design's resource utilization and clock frequencies
- Add I/O power — this is often overlooked but can be significant for designs with many high-speed interfaces
- Add transceiver power — SerDes lanes are power-hungry, especially at 10+ Gbps
- Include power supply efficiency losses — if your board needs 5W, your regulator might draw 6–6.5W from the source
- Apply a 20–30% margin for estimation error and process variation
- Check thermal feasibility — can your enclosure dissipate that much heat at your ambient temperature?
Quick Comparison Table: Typical Mid-Range Designs
| Design | Device | Static (85°C) | Dynamic | Total | Notes |
|---|---|---|---|---|---|
| MCU-like control | Lattice iCE40 | ~20mW | ~50mW | ~70mW | Ultra-low power |
| Sensor processing | Lattice ECP5 | ~200mW | ~500mW | ~700mW | Good for edge |
| Motor control | Xilinx Artix-7 | ~400mW | ~1.5W | ~1.9W | Needs heatsink |
| SDR processing | Xilinx Kintex-7 | ~1W | ~3W | ~4W | Active cooling |
| Video processing | Intel Arria 10 | ~2W | ~5W | ~7W | Forced air required |
| Data acceleration | Xilinx UltraScale+ | ~1W | ~4W | ~5W | Good perf/W at 16nm |
Vendor Power Estimation Tools
For anything beyond rough estimation, use the vendor tools:
- Xilinx: XPE (Xilinx Power Estimator) spreadsheet and Xilinx Power Analyzer in Vivado
- Intel (Altera): Early Power Estimator (EPE) spreadsheet and Power Analyzer in Quartus
- Lattice: Power Calculator in Diamond and Radiant
These tools let you input your specific resource utilization, toggle rates, clock frequencies, and operating conditions to get much more accurate power estimates. They're not perfect, but they're typically within 10–20% of silicon reality when given accurate inputs.
Important: Run these tools before you finalize your board design, not after. Power estimation should be part of your device selection process.
Compare FPGA Power Before You Commit
Running power estimates across multiple FPGAs by hand is tedious. Each vendor has different spreadsheets, different units, and different assumptions baked in. The FPGA Finder & Comparison Tool at semiconductor.tools lets you compare power specs, logic resources, I/O counts, and pricing across devices from Lattice, Intel, and Xilinx in one place.
Want to compare FPGA power consumption side-by-side? Try the FPGA Finder — filter by logic element count, I/O, SerDes speed, and process node. Compare static and dynamic power specifications across vendors in a single table. Free, runs in your browser, no account needed.