You're comparing two FPGAs for your next project. One says it has 25,000 logic elements. The other says 15,000 adaptive logic modules. The first one is cheaper. Done deal, right?
Not even close.
FPGA vendors don't make direct comparison easy. Intel (Altera) uses Adaptive Logic Modules (ALMs). Xilinx (AMD) uses Slice LUTs and Logic Cells. Lattice uses Programmable Functional Units (PFUs). They're all different architectures, they all pack different amounts of logic, and comparing the raw numbers across vendors is like comparing engine displacement across diesel and gas motors — the numbers tell you something, but not everything.
Here's what these terms actually mean, how the architectures differ, and how to make sense of it all when you're selecting an FPGA.
The Basic Building Block: The LUT
At the heart of every FPGA is the Look-Up Table (LUT). It's the fundamental unit of combinational logic.
A LUT is essentially a small memory. A 4-input LUT (the most common size historically) has 4 address inputs and 1 output. It can implement any 4-input Boolean function by storing the truth table in its 16 configuration bits.
Need an AND gate? Store the truth table for AND. Need XOR? Store the XOR truth table. A 4-input LUT can be an AND, OR, XOR, NAND, multiplexer, or any other function of 4 inputs — it's all in how you configure it.
4-input LUT:
Inputs: A, B, C, D (4 address lines = 16 entries)
Output: Y (1 bit)
Can implement ANY function of 4 inputs.
Examples: Y = A AND B AND C AND D
Y = (A XOR B) OR (C AND D)
Y = A ? B : C (multiplexer)
The LUT by itself only handles combinational logic. To build sequential circuits (flip-flops, registers, state machines), each LUT is paired with a flip-flop and some routing multiplexers. This LUT + flip-flop combination is the basic "logic cell" concept.
How Vendors Build on Top of LUTs
Every FPGA vendor takes this basic LUT concept and packages it differently. Here's how the three major vendors do it.
Xilinx (AMD) — Slice and Logic Cell
Xilinx groups four 6-input LUTs (in UltraScale and 7-series) plus 8 flip-flops and some carry logic into a unit called a Slice.
A Logic Cell (LC) is Xilinx's normalized metric — it's defined as one 4-input LUT plus a flip-flop. Since a 6-input LUT can be split into two 4-input LUTs, Xilinx counts each Slice as containing 8 logic cells (though the actual number depends on the specific architecture and usage).
| Xilinx Family | LUT Inputs | LUTs per Slice | Flip-Flops per Slice | Logic Cells per Slice |
|---|---|---|---|---|
| Spartan-6 | 6 | 4 | 8 | ~8 |
| 7-Series (Artix/Kintex/Virtex) | 6 | 4 | 8 | ~8 |
| UltraScale | 6 | 4 | 8 | ~8 |
| UltraScale+ | 6 | 4 | 16 | ~8 |
The move from 4-input to 6-input LUTs was significant. A 6-input LUT can implement any 6-input function, or it can be split into two independent 5-input functions (with shared inputs), or even two 4-input functions. This flexibility means a 6-input LUT can sometimes do the work of two 4-input LUTs.
Intel (Altera) — Adaptive Logic Module (ALM)
Intel's ALM is more flexible than Xilinx's basic LUT structure. Each ALM contains:
- An 8-input combinatorial logic block that can be configured in multiple modes
- Up to 4 flip-flops
- Dedicated carry chain logic
- Arithmetic mode support
The key advantage: an ALM can be split in various ways depending on what you need:
| ALM Mode | What It Implements |
|---|---|
| Normal mode | One function of up to 6 inputs |
| Extended LUT | One function of up to 7 inputs (using two 6-input LUTs with a shared input) |
| Arithmetic mode | Two 4-input functions + carry chain |
| Shared arithmetic | Two functions with shared inputs |
| One 6-input + independent 5-input | Two independent functions |
This adaptiveness is where the "Adaptive" in ALM comes from. The ALM can morph to fit the logic it needs to implement, rather than wasting capacity.
Intel says each ALM is roughly equivalent to 2.5 traditional logic cells in typical designs, though this varies a lot based on the specific logic being implemented.
Lattice — Programmable Functional Unit (PFU)
Lattice uses PFUs in their iCE40 and ECP5 families. Each PFU contains:
- Four 4-input LUTs (iCE40) or four 8-input fracturable LUTs (ECP5/Nexus)
- Flip-flops
- Carry logic
Lattice's iCE40 family is popular in the maker and open-source community specifically because of its simple 4-input LUT architecture and excellent open-source toolchain support (Project IceStorm).
| Lattice Family | LUT Type | LUTs per PFU | Notes |
|---|---|---|---|
| iCE40 | 4-input | 4 | Simple, open-source tools |
| ECP5 | 8-input fracturable | 4 | Higher density |
| Nexus | 8-input fracturable | 4 | Latest family |
Why Does This Matter for Device Selection?
Because "25,000 logic elements" from Vendor A and "15,000 ALMs" from Vendor B might represent very similar amounts of actual logic capacity. Or they might not. It depends on your design.
A Rough Equivalence Table
These are approximate, design-dependent equivalences:
| Vendor | Unit | ≈ Equivalent 4-input LUTs |
|---|---|---|
| Xilinx | 1 Logic Cell | 1 |
| Intel | 1 ALM | ~2.5 |
| Lattice (iCE40) | 1 LUT | 1 |
| Lattice (ECP5) | 1 LUT pair | ~2 |
So a 15,000 ALM Intel FPGA has roughly the logic capacity of a 37,500 logic cell Xilinx FPGA — in theory. In practice, the ratio depends heavily on your design's mix of combinational logic, arithmetic, and register usage.
What Your Design Uses
Different designs stress different parts of the FPGA fabric:
| Design Type | Heavy User Of |
|---|---|
| State machines | LUTs + flip-flops |
| Arithmetic (DSP, filters) | Multipliers + LUTs for adders |
| Memory buffers | Block RAM |
| Data path | LUTs + carry chains |
| Control logic | LUTs, flip-flops scattered |
If your design is mostly state machines and control logic, the LUT count matters most. If you're building DSP pipelines, look at the dedicated multiplier/DSP block count instead — the LUT count is secondary.
Beyond LUTs: The Other Resources
FPGA capacity isn't just about LUTs. A complete comparison needs to account for:
Block RAM (BRAM)
On-chip memory blocks used for FIFOs, buffers, and general storage. Ranges from a few Kbits on small FPGAs to 50+ Mbits on large ones.
DSP Blocks
Dedicated multiplier-accumulator units for signal processing. If you're doing FFTs, FIR filters, or any heavy math, these are critical. Much faster and more power-efficient than implementing multipliers in LUTs.
I/O and SerDes
High-speed transceivers, PLLs, and I/O banks with different voltage standards. These often drive the pin count and package selection more than logic capacity.
Clocking
PLLs and clock management tiles. You need enough to handle all your clock domains.
A Real-World Comparison
Let's compare three mid-range FPGAs at similar price points (~$15-25 in single units):
| Feature | Lattice ECP5-45K | Xilinx Artix-7 XC7A35T | Intel Cyclone 10 GX |
|---|---|---|---|
| Logic | 44K LUTs (4-input equiv) | 33K Logic Cells | 35K ALMs (~87K LC equiv) |
| BRAM | 3.2 Mbit | 1.9 Mbit | 5.5 Mbit |
| DSP | 28 multipliers | 40 multipliers | 84 multipliers |
| PLLs | 2-4 | 5 | 8 |
| I/O | 284 | 210 | 288 |
| Approx. Price (1pc) | ~$15 | ~$20 | ~$25 |
The Intel part looks like it has way more logic — but that's the ALM multiplication factor at work. The real capacity depends on your design.
Practical Advice for Comparing FPGAs
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Don't compare raw unit counts across vendors. An ALM ≠ a Logic Cell ≠ a LUT. Use the rough equivalences above for a first pass.
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Synthesize your design on each target. This is the only reliable comparison. Most FPGA tools have free versions. Run your RTL through each and compare utilization reports.
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Check the resource you'll actually stress. If you need lots of RAM, compare BRAM. If you need multipliers, compare DSP blocks. Don't fixate on LUT count if your design is DSP-heavy.
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Leave margin. Target 60-70% utilization at most. Above 80%, routing becomes difficult, timing closure gets painful, and you have no room for design changes.
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Consider the toolchain. Lattice iCE40 has an excellent open-source flow. Xilinx has Vivado (free WebPACK for smaller parts). Intel has Quartus Prime Lite. Your comfort with these tools should factor into your decision.
The FPGA Finder Tool
Comparing FPGAs across vendors is tedious — different specsheets, different units, different naming conventions. We built the FPGA Finder to make this easier. You can filter by logic capacity, BRAM, DSP blocks, I/O count, and price, and compare parts side by side with normalized metrics.
Want to compare FPGAs without juggling three different datasheets? Try the FPGA Finder — filter by logic capacity, BRAM, DSP blocks, and price across vendors. All specs normalized for fair comparison, running entirely in your browser.
The LUT count is just one piece of the puzzle. Understanding the architecture behind that number helps you make smarter decisions about which FPGA fits your design — not just which one has the biggest number on the datasheet.