Differential Pair PCB Design: Impedance, Length Matching, and Skew

If you're routing USB 2.0, HDMI, PCIe, or really any high-speed interface on a PCB, you're working with differential pairs. And if you're treating them like two single-ended traces that happen to be next to each other... you're going to have signal integrity problems.

Differential signaling rejects common-mode noise, doubles your voltage swing, and lets you push data rates that would be impossible on single-ended traces. But only if you get the PCB design right. Let's cover the three things that matter most: impedance, length matching, and managing skew.

Why Differential Pairs Need Special Treatment

A differential pair is two traces that carry equal and opposite signals. The receiver amplifies the difference between them and rejects anything common to both (common-mode noise).

For this to work, the two traces need to arrive at the receiver at the same time, with the same shape. Any mismatch in length, impedance, or propagation environment degrades the signal.

The key parameters:

Parameter	What It Means	Typical Target
Differential impedance (Zdiff)	Impedance between the two traces of the pair	90Ω (USB), 100Ω (HDMI/Ethernet), 85Ω (PCIe)
Single-ended impedance (Zo)	Impedance of each trace to ground	~50Ω for 100Ω differential
Length mismatch (skew)	Difference in electrical length between D+ and D-	Depends on interface
Coupling	How tightly the two traces interact	Loosely coupled (edge-coupled) is most common

Impedance Calculation

The differential impedance depends on the trace geometry: width, spacing, distance to the reference plane, and dielectric constant of the PCB material.

For an edge-coupled microstrip (traces on an outer layer, reference plane below):

Zdiff ≈ 2 × Zo × (1 - 0.48 × e^(-0.96 × S/H))

Where:

Zo = single-ended impedance of one trace
S = spacing between the two traces
H = height above the reference plane

For an edge-coupled stripline (traces sandwiched between two reference planes):

Zdiff ≈ 2 × Zo × (1 - 0.347 × e^(-2.9 × S/H))

These are approximations. For production designs, use a field solver (Si9000, Saturn PCB, or your CAD tool's built-in impedance calculator).

Worked Example: 100Ω Differential Pair on FR-4

Stackup:

4-layer board
Top layer: signal, 1 oz copper (1.4 mil)
Dielectric: FR-4, Er = 4.2, thickness = 5 mils to ground plane
Ground plane: layer 2

Target: Zdiff = 100Ω

Using a field solver (or iterative calculation):

Trace width: 4.5 mils
Trace spacing: 6.0 mils
This gives Zo ≈ 54Ω per trace, Zdiff ≈ 100Ω

But here's the thing: this assumes FR-4 with Er = 4.2. Actual FR-4 has Er that varies from 4.0 to 4.8 depending on the manufacturer, resin content, and frequency. At 1 GHz, Er might be 4.0. At 100 MHz, it might be 4.5. This variation shifts your impedance by ±5-8%.

Practical tip: Send your impedance requirements to your PCB fab and let them adjust the trace geometry. They know their material's actual dielectric constant. Most fabs provide an impedance control service where they test coupon traces on your panel and report the actual impedance.

Length Matching: How Close Is Close Enough?

The length mismatch between D+ and D- creates skew — the signals arrive at different times. The receiver's common-mode rejection can tolerate some skew, but every interface has its limits.

Skew Budget by Interface

Interface	Data Rate	UI (Unit Interval)	Max Skew	Common Rule
USB 2.0 Hi-Speed	480 Mbps	2.08 ns	1.25 ns	±150 mils
USB 3.2 Gen 1	5 Gbps	200 ps	20 ps	±5 mils
HDMI 2.0	6 Gbps	167 ps	20% of UI = 33 ps	±50 mils
PCIe Gen 3	8 GT/s	125 ps	10-20 ps	±5 mils
SATA III	6 Gbps	167 ps	20 ps	±5 mils
Gigabit Ethernet	1.25 Gbps per pair	800 ps	50 ps	±50 mils

These are guidelines, not hard rules. Check the specific specification document for exact numbers.

Converting Time Skew to Length Mismatch

Signal propagation speed on FR-4:

v = c / √Er_eff

For a microstrip on FR-4 (Er_eff ≈ 3.5):

v = 3 × 10⁸ / √3.5 ≈ 1.6 × 10⁸ m/s ≈ 160 ps/inch

So a 150 mil (0.15 inch) length mismatch creates:

skew = 160 ps/inch × 0.15 inch = 24 ps

That's well within USB 2.0's budget, which is why USB 2.0 is forgiving. But for USB 3.0 at 5 Gbps, 24 ps of skew is already over your budget.

Length Matching Techniques

When you need to add length to one trace, use serpentine tuning (also called accordion tuning). The added bends equalize the electrical length.

Rules for good serpentine tuning:

Keep bends gentle. The radius of each meander should be at least 3× the trace width. Tight bends create impedance discontinuities.
Keep coupling consistent. The spacing between the serpentine and the adjacent trace should match the normal pair spacing where possible.
Place tuning near the mismatch source. If the length mismatch happens at a connector, do the tuning close to the connector rather than in the middle of the route.
Don't tune in tight spaces. Avoid putting serpentine tuning under components or near vias. Keep it in an open area.

Progressive tuning vs. lumped tuning:

Approach	How	Pros	Cons
Lumped	Add all tuning at one point	Easy to implement, compact	Local impedance disruption
Progressive	Small adjustments along the route	Better signal integrity	Takes more space, more complex

For data rates under 5 Gbps, lumped tuning is usually fine. Above 5 Gbps, go progressive.

Via Transitions: A Common Skew Source

When a differential pair transitions between layers through vias, the two traces might not hit their vias at exactly the same point. This creates a length mismatch.

Each via also adds:

Capacitive parasitic (~0.3–0.5 pF per via)
Inductive parasitic (~0.2–0.5 nH per via)
A stub (if it's a through-hole via not connecting all layers)

The stub is a real problem at high speeds. A via stub acts as a resonant structure — at certain frequencies, it reflects energy back. For multi-gigabit signals, use back-drilled vias (the fab drills out the unused portion) or blind/buried vias to eliminate stubs.

For differential pairs transitioning layers:

Place the two vias as a pair, spaced consistently with the differential spacing
Add ground stitching vias nearby (within 50 mils) to provide a return path
Keep the two signal vias the same length (same layer transition)
If one trace needs a few extra mils to reach its via, add the tuning immediately after the via

Spacing Rules: The 3W Guideline

To minimize crosstalk between adjacent differential pairs, follow the 3W rule: the center-to-center spacing between pairs should be at least 3× the trace width.

For a pair with 5-mil traces:

Intra-pair spacing (D+ to D-): 5–7 mils (set by impedance)
Inter-pair spacing: 15 mils minimum center-to-center

If you can afford the board space, 5W spacing is even better. Crosstalk drops off quickly with distance.

Guard traces between pairs are sometimes recommended but rarely needed if you follow the 3W rule. If you do use guard traces, ground them with vias every 200 mils or so. A floating guard trace can actually make crosstalk worse by acting as a coupling antenna.

Practical Design Checklist

Tools and Standards

IPC-2141A — Design Guide for High-Speed Controlled Impedance Circuit Boards
IPC-2152 — Standard for Determining Current-Carrying Capacity in Conductive PCB Designs (also covers impedance considerations)
USB 2.0 Specification — Section 7.1 (USB electrical spec)
PCI Express Card Electromechanical Specification — Differential pair routing rules
Saturn PCB Toolkit — Free impedance calculator with field solver
Si9000 (Polar Instruments) — Industry standard impedance field solver

Calculate your differential pair impedance instantly with the PCB Trace Calculator — enter your stackup (dielectric height, Er, copper weight) and target impedance, and it gives you trace width and spacing for microstrip and stripline configurations.