Vias don't get enough respect. Engineers spend hours calculating trace widths, checking copper weights, and running thermal simulations — then drop a single 0.3 mm via to transition a 5 A power rail between layers. That via is the bottleneck, and nobody checked it.
Here's how via current capacity actually works, how to calculate it, and when you need to start worrying.
Why Vias Are the Weak Link
A via is a copper-plated hole connecting two or more layers. Mechanically and thermally, it's very different from a trace:
- Cross-section is smaller. A typical 0.3 mm finished-hole via with 1 mil (25.4 μm) plating has a cross-sectional area of about 7.5 sq mil — roughly equivalent to a 7.5 mil wide trace. But you'd never route 5 A through a 7.5 mil trace.
- Heat dissipation is different. A trace can spread heat along its length. A via is a narrow cylinder surrounded by FR-4 (a terrible thermal conductor). Heat has fewer places to go.
- Manufacturing variation. Via plating thickness varies more than trace thickness. The 1 mil plating you specified might be 0.8 mil in reality.
The IPC standards that cover trace current capacity (IPC-2221 and IPC-2152) don't give detailed via current charts. This leaves engineers guessing, and that's a problem.
The Basic Calculation
Via current capacity is primarily determined by the cross-sectional area of the copper barrel. Here's how to calculate it:
Step 1: Calculate the Via Cross-Section
A = π × d × t
Where:
d = finished hole diameter
t = copper plating thickness
A = cross-sectional area
Example: A 0.3 mm (12 mil) via with 1 mil (25.4 μm) plating:
A = π × 12 mil × 1 mil = 37.7 sq mil
For reference, a 1 oz copper trace is 1.4 mils thick:
37.7 sq mil ≈ 27 mil wide trace in 1 oz copper
That's surprisingly narrow for a "standard" via.
Step 2: Map to an Equivalent Trace Width
Once you have the cross-sectional area, you can use IPC-2221 or IPC-2152 trace tables to find the current capacity. Treat the via as a trace with the same cross-sectional area.
Using IPC-2221 (external layer, 10°C rise):
| Via Size | Plating | Cross-Section (sq mil) | Approx. Current (10°C rise) |
|---|---|---|---|
| 0.2 mm (8 mil) | 1 mil | 25.1 | ~0.7 A |
| 0.3 mm (12 mil) | 1 mil | 37.7 | ~1.0 A |
| 0.4 mm (16 mil) | 1 mil | 50.3 | ~1.3 A |
| 0.6 mm (24 mil) | 1 mil | 75.4 | ~1.8 A |
| 0.3 mm (12 mil) | 2 mil | 75.4 | ~1.8 A |
| 0.5 mm (20 mil) | 2 mil | 125.7 | ~2.8 A |
These numbers are conservative estimates based on IPC-2221 external layer charts. Real capacity depends on your specific board construction, as we covered in our IPC-2221 vs IPC-2152 comparison.
Step 3: Account for Plating Thickness
The plating thickness is the biggest variable. IPC-2221 specifies a minimum plating of 0.8 mil (20 μm) for Class 2 boards, but many fab houses deliver 1 mil or more.
If your fabricator guarantees 1 mil plating, use it. If you don't know, assume 0.8 mil and add margin.
Heavy copper boards (2 oz, 3 oz, or more) usually have thicker plating too, but don't assume — check with your fab.
The Real Problem: Thermal Relief, Not Just Current
Current capacity is one thing. Thermal performance is another. Vias are often used to carry heat away from components — power ICs, regulators, MOSFETs. In this role, the via's thermal resistance matters more than its current rating.
A single via has a thermal resistance of roughly 150–300°C/W (depending on size, plating, and board thickness). That means 1 W dissipated through one via raises its temperature by 150–300°C. That's catastrophic.
For thermal vias under a QFN or D²PAK package:
- Use multiple vias (4–9 under the thermal pad)
- Larger diameter helps (0.3–0.5 mm is typical)
- Via-in-pad with filled and capped vias for BGA thermal pads
- Connect to internal ground or power planes for heat spreading
A grid of 9 thermal vias, each 0.3 mm, gives you roughly 17–33°C/W thermal resistance. Still significant, but manageable for most power devices.
Multiple Vias for High Current
When your via can't carry the current, use multiple vias. This is standard practice for power supply routing.
Rule of thumb: Divide the total current by the single-via rating, then add 1–2 extra vias for margin.
Example: Routing a 5 A power rail through a 1.6 mm board with 0.3 mm vias (1 mil plating, ~1 A each):
Number of vias = 5 A / 1 A = 5
Add margin: 5 + 2 = 7 vias
Seven 0.3 mm vias in parallel for a 5 A rail. That might seem like a lot, but it's better than a burned via.
Via Placement for Power
When using multiple vias for power:
- Group them close together near the transition point
- Don't spread them along the route — that defeats the purpose
- Place them symmetrically for even current distribution
- Avoid putting vias in high-stress mechanical areas (board mounting holes, flex zones)
Via Arrays: A Quick Reference
| Current Need | Via Size | Plating | Number of Vias | Space Required |
|---|---|---|---|---|
| 1 A | 0.3 mm | 1 mil | 1 | Minimal |
| 2 A | 0.3 mm | 1 mil | 3 | ~1.5 × 1.5 mm |
| 3 A | 0.3 mm | 1 mil | 4–5 | ~2 × 2 mm |
| 5 A | 0.3 mm | 1 mil | 7–8 | ~3 × 3 mm |
| 5 A | 0.5 mm | 2 mil | 3–4 | ~2.5 × 2.5 mm |
| 10 A | 0.5 mm | 2 mil | 6–8 | ~4 × 4 mm |
These are conservative numbers. If you're using IPC-2152 with good thermal management (ground planes near the vias), you can push these higher.
Filled Vias and Via-in-Pad
For dense BGA designs, via-in-pad is common. The via is drilled in the component pad, then filled with epoxy or copper and capped flat. This saves routing space but costs more.
Filled vias have slightly better current capacity than unfilled vias because the fill material (especially copper fill) provides additional cross-section. However, most engineers don't rely on the fill for current carrying — it's primarily a routing density and thermal solution.
Cost impact: Via-in-pad with copper fill adds roughly 10–20% to the board cost. Reserve it for designs that actually need the density.
Signal Integrity Considerations
For high-speed signals, vias create discontinuities. A via adds:
- Parasitic capacitance (typically 0.3–0.8 pF per via)
- Parasitic inductance (typically 0.5–1.0 nH per via)
- Impedance discontinuity at the transition point
For signals under 100 MHz, this rarely matters. For GHz-range signals (DDR3/4, PCIe, USB 3.0, HDMI), via stubs and impedance mismatches are a real concern. Techniques like back-drilling (removing the unused via stub) or blind/buried vias help maintain signal integrity.
But that's a signal integrity topic, not a current capacity one. The key point: don't use oversized vias for high-speed signals just because you're worried about current. Match the via to the signal's actual needs.
Practical Design Rules
Here are the rules I follow for via current capacity:
- Never route more than 1 A through a single standard via (0.3 mm, 1 mil plating) without checking.
- Use multiple vias for anything over 2 A. Calculate the number, add margin.
- Increase plating thickness for power vias. Ask your fab for 1.5–2 mil plating on power layers if possible.
- Via diameter matters less than plating thickness. A 0.3 mm via with 2 mil plating carries roughly the same current as a 0.6 mm via with 1 mil plating, but it takes less board space.
- Thermal vias under power components are not optional. Use via arrays under exposed pads, not single vias.
- Check via temperature in your thermal simulation. If you're running CFD or FEA on your board, include the via array.
A Quick Calculation Example
Let's say you have a buck converter delivering 8 A at 3.3V, and the output needs to transition from the power layer to the component layer through vias.
Using 0.4 mm vias with 1 mil plating (cross-section ≈ 50 sq mil ≈ 1.3 A each):
Vias needed: 8 A / 1.3 A = 6.2 → 7 vias
Add 2 for margin → 9 vias
Arrangement: 3 × 3 grid
Pitch: 0.8 mm (typical)
Total area: ~2 × 2 mm
Nine vias in a 3×3 grid under or near the output inductor pad. That's a small footprint for a reliable 8 A transition.
Want to calculate trace widths and via requirements together? The PCB Trace Width Calculator handles IPC-2221 and IPC-2152 calculations, plus gives you via current estimates for common via sizes.