Choosing an FPGA isn't like picking a microcontroller. With MCUs, you look at clock speed, RAM, and peripherals, check the price, and you're basically done. FPGAs have a dozen more variables, and the wrong pick can sink your project months in — or blow your BOM cost by 5x.
I've gone through the FPGA selection process more times than I'd like to admit. Here's the framework I use, broken down into the decisions that actually matter.
Start With the Right Question
Before looking at a single datasheet, answer these three questions:
- What is the FPGA actually doing? Signal processing? Protocol bridging? Motor control? Custom compute acceleration?
- What's your volume? 10 units for a lab instrument, or 100K units for a consumer product?
- What's your team's experience? Have they used FPGAs before? Which vendor's tools?
These three answers eliminate most of the options immediately.
The Decision Framework
Step 1: Logic Density — How Much Fabric Do You Need?
FPGA capacity is measured in logic elements (LEs), lookup tables (LUTs), or vendor-specific units like ALMs (Intel/Altera) and slices (Xilinx/AMD). These aren't directly comparable across vendors, which is frustrating but manageable.
Here's a rough mapping of project types to logic density:
| Application | Typical LUT Count | Example Devices |
|---|---|---|
| Simple I/O glue logic, protocol bridge | 1K–10K LUTs | Lattice iCE40, MachXO2/3 |
| Motor control, basic DSP | 10K–50K LUTs | Lattice ECP5, Intel Cyclone 10 LP |
| Video processing, medium DSP | 50K–200K LUTs | Intel Cyclone 10 GX, Xilinx Artix-7 |
| High-speed comms, serious DSP | 200K–500K LUTs | Xilinx Kintex-7, Intel Arria 10 |
| Radar, high-end compute, ASIC prototyping | 500K+ LUTs | Xilinx Virtex, Intel Stratix, Agilex |
Rule of thumb: Pick a device with 30–50% more logic than your current design uses. Designs always grow. You'll add features, fix timing, or discover you need more pipeline stages.
If you're porting an existing design, you already know your LUT count. If you're starting fresh, write the critical modules first in HDL, synthesize them, and use that as your baseline.
Step 2: I/O Requirements
This is where many selections go wrong. I/O isn't just about pin count.
Questions to answer:
- How many I/O pins do you need?
- What voltage levels? (1.8V, 2.5V, 3.3V, or mixed?)
- Any differential pairs? (LVDS, MIPI, etc.)
- Any high-speed serial? (PCIe, SATA, USB 3.0, 10GbE?)
- Memory interfaces? (DDR3, DDR4, LPDDR?)
A device might have 200 I/O pins but only 4 differential pair-capable pins, or it might lack the serdes blocks you need for PCIe. Check the I/O bank structure carefully.
Mixed voltage is a common gotcha. If you need both 1.8V and 3.3V I/O, make sure the device has enough I/O banks that you can assign different voltages. Each bank shares a supply voltage — you can't mix voltages within a single bank.
Step 3: Embedded Resources
Modern FPGAs aren't just LUTs and flip-flops. They include hardened IP blocks that can save you a lot of fabric (and power):
| Resource | What It Does | When You Need It |
|---|---|---|
| Block RAM (BRAM) | On-chip memory, typically 18K or 36K bits each | FIFOs, buffers, small caches |
| DSP slices | Hardened multipliers + accumulators | FIR filters, FFT, any multiply-heavy math |
| PLL/MMCM | Clock generation and management | Multiple clock domains, frequency synthesis |
| SerDes transceivers | High-speed serial I/O (1–50+ Gbps) | PCIe, Ethernet, CPRI, JESD204B |
| Hard processor cores | ARM Cortex or RISC-V in the FPGA | SoC designs where you need an OS |
If you're doing DSP work, count your DSP slice requirement early. Synthesizing multipliers from LUTs works but burns fabric fast and runs slower. A 16×16 multiply takes roughly 200 LUTs — a DSP slice handles it in one clock cycle.
Step 4: Power Budget
FPGA power consumption is notoriously hard to estimate pre-silicon. But you can get in the ballpark:
- Small FPGAs (iCE40, MachXO): 50–200 mW typical
- Medium FPGAs (ECP5, Artix-7): 0.5–3 W typical
- Large FPGAs (Kintex-7, Arria 10): 3–15 W typical
- Very large FPGAs (Virtex, Stratix): 10–40 W+
Power depends heavily on:
- Toggle rate of your design (how many flip-flops switch each clock)
- Clock frequency
- I/O activity
- DSP and BRAM utilization
Most vendors provide power estimation spreadsheets (Xilinx Power Estimator, Intel Early Power Estimator). Use them. They're not perfect, but they're better than guessing.
Critical: Don't forget the power supply design. FPGAs often need multiple voltages (core, I/O, auxiliary) with tight tolerance and fast transient response. A 10 W FPGA can need 10–15 A at 0.9 V core. That's not trivial to design.
Step 5: Package and BOM Cost
This is where the rubber meets the road.
Device cost ranges (1K units, approximate):
| Device Family | Price Range |
|---|---|
| Lattice iCE40 | $1–$5 |
| Lattice MachXO3 | $2–$8 |
| Intel Cyclone 10 LP | $5–$25 |
| Lattice ECP5 | $8–$30 |
| Xilinx Artix-7 | $10–$50 |
| Intel Cyclone 10 GX | $15–$60 |
| Xilinx Kintex-7 | $30–$200 |
These are rough numbers. Pricing varies wildly with speed grade, package, and volume.
Don't forget package cost. BGA packages require more PCB layers (4–8 minimum), controlled impedance routing, and X-ray inspection during assembly. A QFP-144 device is much easier (and cheaper) to manufacture than a BGA-484, even if the silicon costs the same.
Step 6: Tooling and Ecosystem
This is the step most engineers want to skip. Don't.
The FPGA toolchain affects your development velocity more than almost anything else:
| Vendor | Tool Suite | Cost | Notes |
|---|---|---|---|
| AMD/Xilinx | Vivado / Vitis | Free (WebPACK) to $3K+ | Good for 7-series and newer. ISE is dead. |
| Intel/Altera | Quartus Prime | Free (Lite) to $4K+ | Solid, well-documented |
| Lattice | Diamond / Radiant | Free | Lightweight, fast compiles |
| Lattice (open source) | Yosys + nextpnr | Free | Great for iCE40 and ECP5 |
If your team has years of Vivado experience, switching to Lattice's open-source flow has a learning curve. If you're starting fresh, Yosys for Lattice devices is surprisingly good and completely free.
Synthesis time matters. A large design in Vivado can take 30–60 minutes for a full implementation. Lattice Diamond might do the same logic density in 5 minutes. When you're iterating on timing closure, that difference adds up fast.
Step 7: Availability and Longevity
Check the product lifecycle before committing. FPGAs targeted at automotive or industrial markets are usually available for 10–15 years. Consumer-grade parts might be obsoleted in 5.
Also check actual lead times and distributor stock. During the 2021–2023 chip shortage, Xilinx 7-series parts had 50+ week lead times while Lattice iCE40 was more available. Availability fluctuates — don't assume today's stock levels are permanent.
Putting It All Together
Here's a worked example. Let's say you're building an industrial vision system that:
- Captures images from a CMOS sensor (MIPI CSI-2)
- Preprocesses frames (debayer, resize, basic filtering)
- Outputs processed data over GigE Vision
- Needs to run in a -40°C to +85°C environment
- Target volume: 5,000 units/year
- Budget: under $30 BOM for the FPGA portion
Walking through the framework:
- Logic density: Image preprocessing pipeline ≈ 30K–80K LUTs (depending on resolution and processing complexity)
- I/O: MIPI CSI-2 input, Gigabit Ethernet MII/GMII, some control GPIO. Need differential pairs.
- Embedded resources: BRAM for line buffers, DSP slices for filtering. No hard processor needed.
- Power: Probably 1–3 W. Manageable.
- Cost target: Under $30 — this rules out Kintex-7 and anything above.
- Tooling: Any vendor works.
Candidates:
- Lattice ECP5 (LFE5U-45F): ~44K LUTs, MIPI D-PHY support, DDR3, ~$12–18 in volume. Good fit.
- Xilinx Artix-7 (XC7A50T): ~52K LUTs, requires external MIPI deserializer, ~$18–25 in volume. Also viable but needs more external components.
The ECP5 wins here because of native MIPI support and lower cost. But if you needed PCIe or SFP+ interfaces, Artix-7 might be better despite the higher price.
Red Flags During Selection
Watch out for these:
- "We'll just get the biggest one." Overprovisioning burns power and money. Size correctly.
- Ignoring the learning curve. If no one on your team has used FPGAs, start with a small Lattice dev board ($20–50) before committing to a $50K development cycle.
- Forgetting configuration flash. FPGAs need external configuration memory. Budget for it ($0.50–2.00).
- Not prototyping early. Get a dev board, build your critical path, measure timing and power. Then finalize your device selection.
Need help comparing FPGAs side by side? The FPGA Finder lets you filter by LUT count, I/O, transceivers, package, and price range — all in one place.