You're starting a new hardware project and the first big architectural decision is staring you in the face: FPGA, ASIC, or MCU? Each has clear strengths and clear trade-offs. Pick wrong and you'll either blow your budget, miss your deadline, or end up with a product that can't do what it needs to do.
Let's break down when each makes sense, with real examples and honest trade-offs.
The Short Version
- MCU (Microcontroller): You need a programmable processor to run software. Best for most projects. Cheap, fast to develop, flexible.
- FPGA (Field-Programmable Gate Array): You need custom hardware-level parallelism, deterministic timing, or protocol-level bit manipulation. More expensive but reprogrammable.
- ASIC (Application-Specific Integrated Circuit): You're building millions of units and need the absolute lowest per-unit cost and highest performance. Massive upfront investment, zero flexibility after tapeout.
That's the 30-second answer. Now let's get into the details.
Microcontrollers: The Default Choice
Modern MCUs are absurdly capable. A $3 STM32 or ESP32 gives you an ARM Cortex core running at 240 MHz, built-in WiFi/BLE, ADCs, DACs, multiple serial interfaces, DMA, and hardware crypto. For the vast majority of products, that's more than enough.
When an MCU Is the Right Call
- You're running sequential code. State machines, protocol stacks, UI logic, data processing pipelines.
- Your timing requirements are in microseconds, not nanoseconds. An interrupt on a modern MCU can respond in under 1 µs.
- You need wireless connectivity. MCUs like the ESP32, nRF52, and STM32WB integrate RF that would be painful to implement on an FPGA.
- You're building fewer than 100,000 units. The development cost of an ASIC doesn't justify itself at low volumes.
- Time to market matters. You can have an MCU prototype running in days. An FPGA takes weeks. An ASIC takes months.
MCU Limitations
- No true parallelism — you're sharing a core between tasks
- Interrupt latency can be unpredictable under heavy load
- Fixed peripheral set — you can't add another UART if all hardware UARTs are in use (you can bitbang, but it's ugly)
- Limited computational throughput for DSP-heavy workloads
Real example: A smart home thermostat with WiFi, a temperature sensor, a display, and a relay. MCU all day. An ESP32 handles this easily for under $5 in components.
FPGAs: Custom Hardware Without the Fab
FPGAs are arrays of configurable logic blocks that you program to implement any digital circuit. You're not writing software that runs on a processor — you're designing hardware that executes in parallel at the gate level.
When an FPGA Is the Right Call
- You need deterministic, sub-nanosecond timing. Motor control, custom communication protocols, sensor interfaces with tight timing windows.
- Massive parallelism. Video processing, digital signal processing, cryptographic acceleration, high-throughput data pipelines.
- Protocol implementation at the bit level. Custom SerDes, non-standard interfaces, or when you need to bitbang at hundreds of MHz.
- You need custom hardware but can't justify an ASIC. Low-to-medium volume products where the FPGA's reprogrammability is a feature.
- Prototyping before ASIC. Many ASIC designs are prototyped on FPGAs first to verify functionality before committing to silicon.
FPGA Trade-offs
- Higher per-unit cost than MCUs ($5-$500+ depending on capacity)
- Steeper learning curve (HDL — Verilog/VHDL — is fundamentally different from C/Python)
- Higher power consumption than MCUs at idle
- Limited analog capabilities (most FPGAs are purely digital)
- Tool chains are expensive and complex (though vendor-free options like Yosys are improving)
FPGA Vendors and Families
| Vendor | Low-End Family | Mid-Range | High-End |
|---|---|---|---|
| Xilinx (AMD) | Spartan (7 series) | Artix/Kintex (7 series) | Virtex/UltraScale+ |
| Intel (Altera) | Cyclone 10 LP | Cyclone 10 GX | Stratix 10 / Agilex |
| Lattice | iCE40 / MachXO3 | ECP5 / CrossLink-NX | — |
| Microchip | IGLOO2 | PolarFire | PolarFire SoC |
Lattice iCE40 is popular in the open-source community because the Yosys + nextpnr toolchain is fully open source. If you're learning FPGA development, the iCE40 (especially the TinyFPGA or iCEstick boards) is a great starting point.
FPGA Cost Reality Check
| Capacity | Approx. Price (1K qty) | Typical Use |
|---|---|---|
| 5K-10K LUTs | $3-$8 | Interface bridging, simple glue logic |
| 20K-50K LUTs | $10-$30 | DSP, motor control, protocol processing |
| 100K-500K LUTs | $30-$150 | Video, SDR, high-speed comms |
| 500K+ LUTs | $150-$500+ | ASIC prototyping, data center acceleration |
Real example: A machine vision system that needs to process 1080p video at 60 fps with real-time edge detection. An MCU can't touch this — you need the parallel processing bandwidth of an FPGA. A Xilinx Artix-7 with ~75K LUTs handles this for around $30-$40.
ASICs: The Nuclear Option
An ASIC is a custom chip designed and fabricated for one specific application. You get exactly the silicon you need — no wasted resources, no unused peripherals, no overhead from programmable routing.
When an ASIC Is the Right Call
- High volume (1M+ units). The $1-5M+ non-recurring engineering (NRE) cost amortizes to pennies per unit.
- Extreme performance requirements. You need the highest possible clock speed, the lowest possible power, or both.
- Form factor constraints. You need maximum functionality in minimum silicon area.
- Power efficiency is critical. ASICs use significantly less power than FPGAs because there's no programmable routing overhead.
- IP protection. A custom chip is much harder to reverse-engineer than firmware on an MCU.
ASIC Trade-offs
- Enormous upfront cost ($1-10M+ depending on process node)
- Long development time (12-24 months from spec to production silicon)
- Zero flexibility after fabrication — a bug means a new chip spin ($$$)
- Access to advanced process nodes (7nm, 5nm, 3nm) is limited to companies with massive budgets
ASIC Cost Breakdown (Rough Estimates)
| Process Node | NRE Cost | Minimum Order | Per-Unit Cost | Who Uses This |
|---|---|---|---|---|
| 180nm | $200K-$500K | 10K units | $0.50-$2 | IoT, simple controllers |
| 65nm | $1M-$3M | 50K units | $1-$5 | Mid-range SoCs |
| 28nm | $3M-$10M | 100K units | $3-$10 | Mobile, networking |
| 7nm/5nm | $20M-$50M+ | 1M+ units | $10-$30 | High-end CPUs/GPUs |
Real example: Apple's A-series and M-series chips. Apple ships hundreds of millions of units per year across iPhones, iPads, and Macs. The billions spent on custom silicon development pays for itself in performance-per-watt that no off-the-shelf chip can match.
The Decision Framework
Here's a practical flow chart for your next project:
- Does it need to run software with an OS or complex firmware? → MCU
- Does it need true parallel processing or sub-µs deterministic timing? → FPGA (or MCU + FPGA)
- Are you shipping more than 1M units and can afford $1M+ NRE? → ASIC
- Is power consumption the #1 priority and volume justifies it? → ASIC
- Still unsure? → Start with an MCU. You can migrate to FPGA or ASIC later if needed.
The Hybrid Approach: SoC FPGAs
Some chips combine an ARM MCU core with FPGA fabric on the same die. Examples:
- Xilinx Zynq (Cortex-A9/A53 + FPGA fabric)
- Intel Cyclone V SoC (Cortex-A9 + FPGA fabric)
- Microchip PolarFire SoC (RISC-V + FPGA fabric)
These let you run Linux on the processor core while handling real-time tasks in the FPGA fabric. They're popular in industrial control, automotive, and software-defined radio applications.
Comparison Table
| Factor | MCU | FPGA | ASIC |
|---|---|---|---|
| Unit cost (low vol) | $1-$10 | $5-$100 | N/A (NRE dominates) |
| Unit cost (high vol) | $0.50-$5 | $3-$50 | $0.10-$5 |
| NRE cost | $0-$10K | $5K-$50K | $1M-$50M+ |
| Time to prototype | Days-weeks | Weeks-months | Months-years |
| Power (idle) | µW-mW | mW-W | µW-mW |
| Performance ceiling | Medium | High | Highest |
| Flexibility after build | Firmware updates | Reprogram | None |
| Design complexity | Low-medium | High | Very high |
| Team size needed | 1-3 engineers | 2-5 engineers | 10-50+ engineers |
Common Myths
"FPGAs are always faster than MCUs." Not necessarily. For sequential tasks, a 300 MHz Cortex-M7 will outperform a 100 MHz FPGA implementation. FPGAs win on parallelism, not raw clock speed.
"ASICs are always cheaper at volume." Only if your volume justifies the NRE. At 100K units with a $5M NRE, each unit carries $50 of NRE cost alone. The crossover point depends heavily on the specific design.
"You can't use an MCU for real-time control." Modern MCUs with proper interrupt priorities and DMA can handle most real-time tasks. FPGAs are only necessary when you need sub-microsecond deterministic response.
Trying to pick the right FPGA for your design? The FPGA Selection Tool lets you filter by LUT count, I/O, power budget, and price to find the right device from Xilinx, Intel, Lattice, and Microchip. No more digging through parametric search tables — just enter your requirements and compare options side by side.